Newly manufactured digital circuits require testing of the combinational logic. One conventional testing technique is to generate a number of scan vectors and input them to the circuit. After passing through the circuit, the values are sampled and compared with expected results, based upon the configuration of the combinational logic. An automatic test pattern generation (ATPG) tool may be used to assist the process. However, if the circuit contains random access memory (RAM), the testing process is complicated. For example, some combinational logic may feed the various inputs to the RAM and the output of the RAM may feed more combinational logic. Unfortunately, the output of the RAM during this testing process is extremely difficult to predict. Consequently, it is very difficult to test the combinational logic that feeds or is fed by the RAM.
One conventional method of such testing provides for cases resulting in unknown values. For example, if RAM negatively impacted testing, the expected value at the output of the circuit will be indeterminate. Otherwise, a definite one or zero is expected. Accounting for the unknown case requires a doubling of the amount of memory in the ATPG tool. Consequently, this greatly increases testing costs. Additionally, the combinational logic along the unknown path is untested. Furthermore, some conventional testing tools do not allow for unknown states. Other testing tools may allow for unknown states when a limited number of test vectors are used, for example, 256,000. However, if more test vectors are used, the tool is unable to handle unknown values.
Another conventional method of testing combinational logic when RAM is present is a partial scan method, which eliminates from the scan chain the combinational logic that the RAM output feeds. Unfortunately, this method decreases the ability to detect manufacturing defects. Consequently, this reduces the quality of the parts shipped.
Another conventional testing method places a series of multiplexers before each RAM, which allow bypassing the RAMs when in testing mode. This method may lead to covering combinational logic that feeds and is fed by the RAMs. However, the additional multiplexers add significantly to the cost per part by adding to the die level resources. Furthermore, during non-test operation the signal must still pass through the added multiplexers to get to the RAMs. Therefore, this may delay the critical path if the RAM to read data is the longest path in the circuit.